Vertical power transistor device

ABSTRACT

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

RELATED APPLICATIONS

The present application is a reissue of U.S. Pat. No. 9,331,197, issuedMay 3, 2016, and entitled VERTICAL POWER TRANSISTOR DEVICE. Thedisclosure of which is incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to power transistor devices, and inparticular to power metal-oxide-semiconductor field-effect transistor(MOSFET) devices.

BACKGROUND

A power metal-oxide-semiconductor field-effect transistor (MOSFET) is atype of transistor that is adapted for use in high power applications.Generally, a power MOSFET device has a vertical structure, wherein asource and gate contact are located on a first surface of the MOSFETdevice that is separated from a drain contact by a drift layer formed ona substrate. Vertical MOSFETS are sometimes referred to as verticaldiffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Dueto their vertical structure, the voltage rating of a power MOSFET is afunction of the doping and thickness of the drift layer. Accordingly,high voltage power MOSFETs may be achieved with a relatively smallfootprint.

FIG. 1 shows a conventional power MOSFET device 10. The conventionalpower MOSFET device 10 includes a substrate 12, a drift layer 14 formedover the substrate 12, one or more junction implants 16 in the surfaceof the drift layer 14 opposite the substrate, and a junction gate fieldeffect transistor (JFET) region 18 between each one of the junctionimplants 16. Each one of the junction implants 16 is formed by an ionimplantation process, and includes a deep well region 20, a base region22, and a source region 24. Each deep well region 20 extends from acorner of the drift layer 14 opposite the substrate 12 downwards towardsthe substrate 12 and inwards towards the center of the drift layer 14.The deep well region 20 may be formed uniformly or include one or moreprotruding regions, as shown in FIG. 1. Each base region 22 is formedvertically from the surface of the drift layer 14 opposite the substrate12 down towards the substrate 12 along a portion of the inner edge ofeach one of the deep well regions 20. Each source region 24 is formed ina shallow portion on the surface of the drift layer 14 opposite thesubstrate 12, and extends laterally to overlap a portion of the deepwell region 20 and the base region 22, without extending over either.The JFET region 18 defines a channel width 26 between each one of thejunction implants 16.

A gate oxide layer 28 is positioned on the surface of the drift layer 14opposite the substrate 12, and extends laterally between a portion ofthe surface of each source region 24, such that the gate oxide layer 28partially overlaps and runs between the surface of each source region 24in the junction implants 16. A gate contact 30 is positioned on top ofthe gate oxide layer 28. Two source contacts 32 are each positioned onthe surface of the drift layer 14 opposite the substrate 12 such thateach one of the source contacts 32 partially overlaps both the sourceregion 24 and the deep well region 20 of one of the junction implants16, respectively, and does not contact the gate oxide layer 28 or thegate contact 30. A drain contact 34 is located on the surface of thesubstrate 12 opposite the drift layer 14.

In operation, when a biasing voltage is not applied to the gate contact30 and the drain contact 34 is positively biased, a junction betweeneach deep well region 20 and the drift layer 14 is reverse biased,thereby placing the conventional power MOSFET 10 in an OFF state. In theOFF state of the conventional power MOSFET 10, any voltage between thesource and drain contact is supported by the drift layer 14. Due to thevertical structure of the conventional power MOSFET 10, large voltagesmay be placed between the source contacts 32 and the drain contact 34without damaging the device.

FIG. 2 shows operation of the conventional power MOSFET 10 when thedevice is in an ON state. When a positive bias is applied to the gatecontact 30 of the conventional power MOSFET 10, an inversion layerchannel 36 is formed at the surface of the drift layer 14 underneath thegate contact 30, thereby placing the conventional power MOSFET 10 in anON state. In the ON state of the conventional power MOSFET 10, current(shown by the shaded region in FIG. 2) is allowed to flow from each oneof the source contacts 32 through the inversion layer channel 36 andinto the JFET region 18 of the drift layer 14. Once in the JFET region18, current flows downward through the drift layer 14 towards the draincontact 34. An electric field presented by junctions formed between thedeep well region 20, the base region 22, and the drift layer 14constricts current flow in the JFET region 18 into a JFET channel 38having a JFET channel width 40. At a certain spreading distance 42 fromthe inversion layer channel 36 when the electric field presented by thejunction implants 16 is diminished, the flow of current is distributedlaterally, or spread out in the drift layer 14, as shown in FIG. 2. TheJFET channel width 40 and the spreading distance 42 determine theinternal resistance of the power MOSFET 10, thereby dictating theperformance of the device. A conventional power MOSFET 10 generallyrequires a channel width 26 of 3 microns or wider in order to sustain anadequate JFET channel width and 40 spreading distance 42 for properoperation of the device.

The electric field formed by the junctions between the deep well region20, the base region 22, and the drift layer 14 radiates through the gateoxide layer 28, thereby physically degrading the gate oxide layer 28over time. Eventually, the electric field will cause the gate oxidelayer 28 to break down, and the conventional power MOSFET 10 will ceaseto function.

Accordingly, a power MOSFET is needed that is capable of handling highvoltages in the OFF state while maintaining a low ON state resistanceand having an improved longevity.

SUMMARY

The present disclosure relates to a transistor device including asubstrate, a drift layer over the substrate, and a spreading layer overthe drift layer. The spreading layer includes a pair of junctionimplants separated by a junction gate field effect (JFET) region. Eachone of the junction implants may include a deep well region, a baseregion, and a source region. The transistor device further includes agate oxide layer, a gate contact, a pair of source contacts, and a draincontact. The gate oxide layer is on a portion of the spreading layersuch that the gate oxide layer partially overlaps and runs between eachsource region of each junction implant. The gate contact is on top ofthe gate oxide layer. Each one of the source contacts are on a portionof the spreading layer such that each source contact partially overlapsboth the source region and the deep well region of each junctionimplant, respectively. The drain contact is on the surface of thesubstrate opposite the drift layer.

According to one embodiment, the spreading layer has a graded dopingprofile, such that the doping concentration of the spreading layerdecreases in proportion to the distance of the point in the spreadinglayer from the JFET region.

According to an additional embodiment, the spreading layer includesmultiple layers, each having a different doping concentration thatprogressively decreases in proportion to the distance of the layer fromthe JFET region.

By placing a spreading layer over the drift layer, the space betweeneach junction implant, or length of the JFET region, can be reducedwhile simultaneously maintaining or reducing the ON resistance of thedevice. By reducing the space between each junction implant, a largerportion of the electric field generated during reverse bias of thetransistor device is terminated by each one of the junction implants,thereby reducing the electric field seen by the gate oxide layer andincreasing the longevity of the device.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1 shows a schematic representation of a conventional power MOSFETdevice.

FIG. 2 shows details of the operation of the conventional power MOSFETdevice shown in FIG. 1.

FIG. 3 shows a power MOSFET device according to one embodiment of thepresent disclosure.

FIG. 4 shows details of the operation of the power MOSFET device shownin FIG. 3 according to one embodiment of the present disclosure.

FIG. 5 shows an alternative embodiment of the power MOSFET device shownin FIG. 3.

FIGS. 6-15 illustrate a process for manufacturing the power MOSFETdevice shown in FIG. 3.

FIG. 16 shows a graph indicating performance improvements achieved bythe power MOSFET device shown in FIG. 3.

FIG. 17 shows a graph indicating longevity improvements achieved by thepower MOSFET device shown in FIG. 3.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

Turning now to FIG. 3, a power MOSFET device 44 is shown according toone embodiment of the present disclosure. The power MOSFET device 44includes a substrate 46, a drift layer 48 formed over the substrate 46,a spreading layer 50 formed over the drift layer 48, one or morejunction implants 52 in the surface of the spreading layer 50 oppositethe drift layer 48, and a junction gate field effect transistor (JFET)region 54 between each one of the junction implants 52. Each one of thejunction implants 52 may be formed by an ion implantation process, andmay include a deep well region 56, a base region 58, and a source region60. Each deep well region 56 extends from a corner of the spreadinglayer 50 opposite the drift layer 48 downwards towards the drift layer48 and inwards towards the center of the spreading layer 50. The deepwell region 56 may be formed uniformly or include one or more protrudingregions. Each base region 58 is formed vertically from the surface ofthe spreading layer 50 opposite the drift layer 48 downwards towards thedrift layer 48 along a portion of the inner edge of each one of the deepwell regions 56. Each source region 60 is formed in a shallow portion onthe surface of the spreading layer 50 opposite the drift layer 48, andextends laterally to overlap a portion of the deep well region 56 andthe base region 58, without extending over either. The JFET region 54defines a channel width 62 between each one of the junction implants 52.

A gate oxide layer 64 is positioned on the surface of the spreadinglayer 50 opposite the drift layer 48, and extends laterally between aportion of the surface of each source region 60, such that the gateoxide layer 64 partially overlaps and runs between the surface of eachsource region 60 in the junction implants 52. A gate contact 66 ispositioned on top of the gate oxide layer 64. Two source contacts 68 areeach positioned on the surface of the spreading layer 50 opposite thedrift layer 48 such that each one of the source contacts 68 partiallyoverlaps both the source region 60 and the deep well region 56 of thejunction implants 52, respectively, and does not contact the gate oxidelayer 64 or the gate contact 66. A drain contact 70 is located on thesurface of the substrate 46 opposite the drift layer 48.

In operation, when a biasing voltage is not applied to the gate contact66 and the drain contact 70 is positively biased, a junction betweeneach deep well region 56 and the spreading layer 50 is reverse biased,thereby placing the power MOSFET 44 in an OFF state. In an OFF state ofthe power MOSFET 44, any voltage between the source and drain contact issupported by the drift layer 48 and the spreading layer 50. Due to thevertical structure of the power MOSFET 44, large voltages may be placedbetween the source contacts 68 and the drain contact 70 without damagingthe device.

FIG. 4 shows the operation of the power MOSFET 44 when the device is inan ON state. When a positive bias is applied to the gate contact 66 ofthe power MOSFET 44, an inversion layer channel 72 is formed at thesurface of the spreading layer 50 underneath the gate contact 66,thereby placing the power MOSFET 44 in an ON state. In the ON state ofthe power MOSFET 44, current (shown by the shaded region in FIG. 4) isallowed to flow from each one of the source contacts 68 through theinversion layer channel 72 and into the JFET region 54. Once in the JFETregion 54, current flows downward through the spreading layer 50 towardsthe drain contact 70. An electric field presented by the junctionsformed between the deep well region 56, the base region 58, and thespreading layer 50 constricts current flow in the JFET region 54 into aJFET channel 74 having a JFET channel width 76.

At a certain spreading distance 78 from the inversion layer channel 72when the electric field presented by the junction implants 52 isdiminished, the flow of current is distributed laterally, or spread out,in the spreading layer 50, as shown in FIG. 4. The spreading layer 50 isdoped in such a way to decrease resistance in the spreading layer 50,thereby mitigating the effects of the electric field by increasing theJFET channel width 76 and decreasing the spreading distance 78. Byincreasing the JFET channel width 76 and decreasing the spreadingdistance 78, the spreading layer 50 significantly reduces the ONresistance of the power MOSFET 44. For example, the ON resistance of thepower MOSFET 44 may be about 2.2 mΩ/cm² when the device is rated tohandle 1200V and about 1.8 mΩ/cm² when the device is rated to handle600V.

By reducing the ON resistance of the power MOSFET 44, the spreadinglayer 50 allows for a reduction of the channel width 62 between each oneof the junction implants 52. Reducing the channel width 62 of the powerMOSFET 44 not only improves the footprint of the device, but also thelongevity. As each one of the junction implants 52 is moved closer toone another, a larger portion of the electric field generated by thejunctions between the deep well region 56, the base region 58, and thespreading layer 50 is terminated by the opposite junction implant 52.Accordingly, the electric field seen by the gate oxide layer 64 issignificantly reduced, thereby resulting in improved longevity of thepower MOSFET 44. According to one embodiment, the channel width 62 ofthe power MOSFET 44 is less than 3 microns.

The power MOSFET 44 may be, for example, a silicon carbide (SiC),gallium arsenide (GaAs), or gallium nitride (GaN) device. Those ofordinary skill in the art will appreciate that the concepts of thepresent disclosure may be applied to any materials system. The substrate46 of the power MOSFET 44 may be about 180-350 microns thick. The driftlayer 48 may be about 3.5-12 microns thick, depending upon the voltagerating of the power MOSFET 44. The spreading layer 50 may be about1.0-2.5 microns thick. Each one of the junction implants 52 may be about1.0-2.0 microns thick. The JFET region 54 may be about 0.75-1.5 micronsthick.

According to one embodiment, the spreading layer 50 is an N-doped layerwith a doping concentration from about 2×10¹⁷ cm⁻³ to 5×10¹⁶ cm⁻³. Thespreading layer 50 may be graded, such that the portion of the spreadinglayer 50 closest to the drift layer 48 has a doping concentration about5×10¹⁶ cm⁻³ that is graduated as the spreading layer 50 extends upwardsto a doping concentration of about 2×10¹⁷ cm⁻³. According to anadditional embodiment, the spreading layer 50 may comprise multiplelayers. The layer of the spreading layer 50 closest to the drift layer48 may have a doping concentration about 5×10¹⁶ cm⁻³. The dopingconcentration of each additional layer in the spreading layer maydecrease in proportion to the distance of the layer from the JFET region54. The layer of the spreading layer 50 closest to the drift layer 48may have a doping concentration about 2×10¹⁷ cm⁻³.

The JFET region 54 may be an N-doped layer with a doping concentrationfrom about 1×10¹⁶ cm⁻³ to 2×10¹⁷ cm⁻³. The drift layer 48 may be anN-doped layer with a doping concentration from about 6×10¹⁵ cm⁻³ to1.5×10¹⁶ cm⁻³. The deep well region 56 may be a heavily P-doped regionwith a doping concentration from about 5×10¹⁷ cm⁻³ to 1×10²⁰ cm⁻³. Thebase region 58 may be a P-doped region with a doping concentration fromabout 5×10¹⁶ cm⁻³ to 1×10¹⁹cm⁻³. The source region 60 may be an N-dopedregion with a doping concentration from about 1×10¹⁹ cm⁻³ to 1×10²¹cm⁻³. The N doping agent may be nitrogen, phosphorous, or any othersuitable element, as will be appreciated by those of ordinary skill inthe art. The P doping agent may be aluminum, boron, or any othersuitable element, as will be appreciated by those of ordinary skill inthe art.

The gate contact 66, the source contacts 68, and the drain contact 70may be comprised of multiple layers. For example, each one of thecontacts may include a first layer of nickel or nickel-aluminum, asecond layer of titanium over the first layer, a third layer oftitanium-nickel over the second layer, and a fourth layer of aluminumover the third layer. Those of ordinary skill in the art will appreciatethat the gate contact 66, the source contacts 68, and the drain contact70 may be formed of any suitable material.

FIG. 5 shows the power MOSFET 44 according to an additional embodimentof the present disclosure. The power MOSFET 44 shown in FIG. 5 issubstantially similar to that of FIG. 3, but further includes a channelRe-growth layer 80 between the gate oxide layer 64 and the spreadinglayer 50. The channel re-growth layer 80 is provided to lower thethreshold voltage of the power MOSFET 44. Specifically, the deep wellregion 56, due to a heavy level of doping, may raise the thresholdvoltage of the power MOSFET 44 to a level that inhibits optimumperformance. Accordingly, the channel re-growth layer 80 may offset theeffects of the deep well region 56 in order to lower the thresholdvoltage of the power MOSFET 44. The channel re-growth layer 80 may be anN-doped region with a doping concentration from about 1×10¹⁵ cm⁻³ to1×10¹⁷ cm⁻³

FIGS. 6-15 illustrate a process for manufacturing the power MOSFET 44shown in FIG. 3. First, as illustrated by FIG. 6, the drift layer 48 isgrown on top of the substrate 46. Those of ordinary skill in the artwill recognize that any suitable growth process may be used to producethe drift layer 48 without departing from the principles of the presentdisclosure. For example, a chemical vapor deposition process may be usedto form the drift layer 48.

Next, as illustrated by FIG. 7, the spreading layer 50 is grown on topof the drift layer 48. As discussed above, any suitable growth processmay be used to create the spreading layer 50 without departing from theprinciples of the present disclosure. According to one embodiment, thespreading layer 50 is grown such that it includes a graded dopingprofile.

Next, as illustrated by FIG. 8, the deep well region 56 of each one ofthe junction implants 52 is implanted in the spreading layer 50. As willbe appreciated by those of ordinary skill in the art, the deep wellregions 56 may be implanted by any suitable implantation process. Forexample, an ion implantation process may be used to form the deep wellregions 56. The base regions 58 are then implanted, as illustrated byFIG. 9, followed by the source regions 60, as illustrated by FIG. 10.

Next, as illustrated by FIG. 11, the JFET region 54 is implanted. Asdiscussed above, any suitable implantation process may be used to createthe JFET region 54 without departing from the principles of the presentdisclosure. Additionally, although not illustrated, the JFET region 54may alternatively be created by a growth process.

Next, as illustrated by FIG. 12, the gate oxide layer 64 is formed ontop of the spreading layer 50, such that the gate oxide layer 64partially overlaps and runs between the surface of each source region 60in the junction implants 52. In FIG. 13, the gate contact 66 is formedon top of the gate oxide layer 64. The source contacts 68 are thenformed on the surface of the spreading layer 50 such that each one ofthe source contacts 68 partially overlaps both the source region 60 andthe deep well region 56 of the junction implants 52, respectively, anddoes not contact the gate oxide layer 64 or the gate contact 66, asillustrated by FIG. 14. Finally, in FIG. 15, the drain contact 70 isprovided on the surface of the substrate 46 opposite the drift layer 48.

FIG. 16 is a chart depicting the effect of the spreading layer 50 on theON resistance of the power MOSFET 44. As shown, the spreading layerprovides about a 20% decrease in the ON resistance of the device.

FIG. 17 is a chart depicting the effect of the spreading layer 50 on theelectric field seen by the gate oxide layer 64. Because the spreadinglayer 50 allows a reduction in channel width 62 without impeding theperformance of the power MOSFET 44, up to 26% of the electric field seenby the gate oxide layer 64 may be terminated by the opposing junctionimplants 52, thereby significantly increasing the longevity of thedevice.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A transistor device comprising a gate, a source,and a drain, wherein the gate and the source are separated from thedrain by at least a JFET region, a spreading layer including a gradeddoping profile, and a drift layer, wherein a doping concentration of thespreading layer varies more than a factor of about 10² cm⁻³ between theJFET region and the drift layer, a thickness of the JFET region isbetween 0.75 μm and 1.5 μm, a pair of junction implants is in thespreading layer such that the pair of junction implants is separated bythe JFET region, the pair of junction implants is provided to a depthbetween 1.0 μm and 2.0 μm measured from a surface of the spreading layeropposite the drift layer, the doping concentration of the spreadinglayer increases as a distance from the drift layer increases, and athickness of the spreading layer is between 1.0 μm and 2.5 μm.
 2. Thetransistor device of claim 1 wherein the JFET region, the spreadinglayer, and the drift layer comprise silicon carbide.
 3. The transistordevice of claim 1 wherein the transistor device is a vertically disposedmetal-oxide-semiconductor field-effect transistor (MOSFET).
 4. Thetransistor device of claim 1 wherein the JFET region has a first dopingconcentration, the spreading layer has a second doping concentrationthat is different from the first doping concentration, and the driftlayer has a third doping concentration that is different from the firstdoping concentration and the second doping concentration.
 5. Thetransistor device of claim 4 wherein the spreading layer has a dopingconcentration in the range of approximately 2×10¹⁷ cm⁻³ to approximately5×10¹⁶ cm⁻³.
 6. The transistor device of claim 4 wherein the JFET regionhas a doping concentration in the range of approximately 1×10¹⁶ cm⁻³ toapproximately 2×10¹⁷ cm⁻³.
 7. The transistor device of claim 1 wherein athickness of the JFET region is in the range of approximately 0.75microns to approximately 1 micron drift layer is in the range ofapproximately 3.5 μm to approximately 12 μm.
 8. The transistor device ofclaim 1 wherein a thickness of the spreading layer is in the range ofapproximately 1.0 microns to approximately 2.5 microns.
 9. Thetransistor device of claim 1 wherein a thickness of the drift layer isin the range of approximately 3.5 microns to approximately 12 microns.10. The transistor device of claim 1 wherein an internal resistance ofthe transistor device is less than approximately 2.2 mΩ/cm².
 11. Thetransistor device of claim 1 wherein the transistor device is adapted tosupport a voltage between the source and the drain of at least 600Vwhile in an OFF state, and further wherein the transistor device has aninternal resistance of less than approximately 1.8 mΩ/cm².
 12. Thetransistor device of claim 1 wherein the transistor device is adapted tosupport a voltage between the source and the drain of at least 1200Vwhile in an OFF state, and further wherein the transistor device has aninternal resistance of less than approximately 2.2 mΩ/cm².
 13. Atransistor device comprising: a substrate; a drift layer on thesubstrate; a spreading layer on the drift layer, the spreading layerhaving a graded doping profile such that a doping concentration of thespreading layer varies more than a factor of about 10² cm⁻³ between aJFET region and the drift layer, the doping concentration of thespreading layer increases as a distance from the drift layer increases,a thickness of the spreading layer is between 1.0 μm and 2.5 μm, and athickness of the JFET region is between 0.75 μm and 1.5 μm; a pair ofjunction implants in the spreading layer and separated by the JFETregion, each one of the pair of junction implants comprising a deep wellregion, a base region, and a source region such that a depth of the deepwell region as measured from a surface of the spreading layer oppositethe drift layer is between 1.0 μm and 2.0 μm; a gate contact and asource contact on the spreading layer, such that the gate contactpartially overlaps and runs between each source region in the pair ofjunction implants; and a drain contact on the substrate opposite thedrift layer.
 14. The transistor device of claim 13 further comprising agate oxide layer between the gate contact and the spreading layer. 15.The transistor device of claim 13 wherein the source contact is dividedinto two sections, and each section of the source contact is on aportion of the spreading layer such that each section of the sourcecontact partially overlaps both the source region and the deep wellregion of each one of the pair of junction implants, respectively. 16.The transistor device of claim 13 wherein the transistor device is avertically disposed metal-oxide-semiconductor field-effect transistor(MOSFET).
 17. The transistor device of claim 13 wherein the drift layerand the spreading layer comprise silicon carbide.
 18. The transistordevice of claim 13 wherein a width of the JFET region is approximately 3microns μm or less.
 19. The transistor device of claim 18 wherein aninternal resistance of the transistor device is less than approximately2.2 mΩ/cm².
 20. The transistor device of claim 13 wherein the transistordevice is adapted to support a voltage between the source contact andthe drain contact of at least 600V while in an OFF state, and furtherwherein the transistor device has an internal resistance of less thanapproximately 1.8 mΩ/cm².
 21. The transistor device of claim 13 whereinthe transistor device is adapted to support a voltage between the sourcecontact and the drain contact of at least 1200V while in an OFF state,and further wherein the transistor device has an internal resistance ofless than approximately 2.2 mΩ/cm².
 22. The transistor device of claim13 wherein a thickness of the drift layer is in the range ofapproximately 3.5 microns to approximately 12 microns.
 23. Thetransistor device of claim 13 wherein a thickness of the spreading layeris in the range of approximately 1.0 microns to approximately 2.5microns.
 24. The transistor device of claim 13 wherein a thickness ofthe JFET region is in the range of approximately 0.75 microns toapproximately 1.0 microns drift layer is in a range of approximately 3.5μm to approximately 12 μm.
 25. The transistor device of claim 13 whereina thickness of each one of the pair of junction implants is in the rangeof approximately 1.0 microns to approximately 2.0 microns.
 26. A methodfor manufacturing a transistor device, the method comprising: providinga substrate; providing a drift layer on the substrate; providing aspreading layer on the drift layer such that the spreading layer has athickness between 1.0 μm and 2.5 μm and the spreading layer has a gradeddoping profile wherein a doping concentration of the spreading layerincreases as a distance from the drift layer increases such that a ratioof the doping concentration at a surface of the spreading layer adjacentto the drift layer to the doping concentration at a surface of thespreading layer opposite the drift layer is 1:x where x is greater thanor equal to 2; providing a pair of junction implants in the spreadinglayer such that each of the pair of junction implants is laterallyseparated from one another and a depth of the pair of junction implantsas measured from a surface of the spreading layer opposite the driftlayer is between 1.0 μm and 2.0 μm; providing a junction field effecttransistor (JFET) region between the pair of junction implants, the JFETregion having a thickness between 0.75 μm and 1.5 μm; providing a gateoxide layer on the spreading layer opposite the drift layer; providing agate contact on the gate oxide layer; providing a source contact on thespreading layer over at least one of the pair of junction implants; andproviding a drain contact on the substrate opposite the drift layer. 27.The method of claim 26 wherein the substrate, the drift layer, and thespreading layer are silicon carbide.
 28. The method of claim 26 whereinx is less than or equal to
 4. 29. The method of claim 26 wherein thespreading layer is provided such that the doping concentration at thesurface of the spreading layer adjacent to the drift layer is 5×10¹⁶cm⁻³and the doping concentration at the surface of the spreading layeropposite the drift layer is 2×10¹⁷ cm⁻³.
 30. The method of claim 26wherein providing the spreading layer comprises providing a plurality oflayers, each having a different doping concentration to provide thegraded doping profile of the spreading layer.
 31. The method of claim 26wherein the substrate, the drift layer, the spreading layer, and thepair of junction implants are provided such that a distance between thepair of junction implants is less than 3 μm, an on-state resistance ofthe transistor device is between 1.8 mΩ/cm² and 2.2 mΩ/cm², and ablocking voltage of the transistor device is between 600 volts and 1200volts.
 32. The transistor device of claim 31 wherein x is less than orequal to 4.